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MX88L250EC
Revision: 0.03A 2001/10/12
MX88L250EC-X MX88L250EC-S MX88L250EC-D Data Sheet
1
MX88L250EC
Revision: 0.03A 2001/10/12
Table of Contentsd
TABLE OF CONTENTSD........................................................................................................................................2 GENERAL DESCRIPTION ...................................................................................................................................4 APPLICATIONS .....................................................................................................................................................4 FEATURES .............................................................................................................................................................4 GENERAL FEATURES ...............................................................................................................................................4 INPUT.....................................................................................................................................................................4 OUTPUT .................................................................................................................................................................5 CPU INTERFACE.....................................................................................................................................................5 POWER...................................................................................................................................................................5 CHIP BLOCK DIAGRAM .....................................................................................................................................6 SYSTEM BLOCK DIAGRAM FOR LCD MONITOR ( TTL AND PANELLINK / LVDS INTERFACED )....7 ANALOG INTERFACE LCD MONITOR ............................................................................................................7 DIGITAL INTERFACE LCD MONITOR.............................................................................................................7 MX88L250EC-X, MX88L250EC-S 128P PIN CONFIGURATIONS ....................................................................8 MX88L250EC-D 160P PIN CONFIGURATIONS .................................................................................................9 GENERAL DESCRIPTION .................................................................................................................................10 VIP (VIDEO INPUT PROCESSOR) FUNCTION DESCRIPTION.......................................................................................10 VOP (VIDEO OUTPUT PROCESSOR) FUNCTION DESCRIPTION..................................................................................10 BIU (BUS INTERFACE UNIT) FUNCTION DESCRIPTION ............................................................................................10 PIN DESCRIPTION..............................................................................................................................................11 CPU INTERFACE PINS: (8 / 16 PINS) ......................................................................................................................11 INPUT INTERFACE PINS: (29 / 53 PINS)................................................................................................................... 11 LCD INTERFACE PINS: (53 PINS) ...........................................................................................................................12 INTERNAL VCG INTERFACE PINS: (2 PINS) ............................................................................................................13 OTHER INTERFACE PINS: (6 PINS) ..........................................................................................................................13 EXTERNAL CLOCK INPUT INTERFACE PINS: (2 PIN)................................................................................................. 14 POWER PINS: (28 PINS) DUAL POWER 3.3 / 2.5 VOLTS, 5 VOLT TOLERANT INPUTS................................................... 14 AC CHARACTERISTICS ....................................................................................................................................15 1. INPUT SIGNAL ........................................................................................................................................15 2. OUTPUT SIGNAL................................................................................................................................................ 16 3. DIRECT CPU INTERFACE...................................................................................................................................17 4. SERIAL BUS INTERFACE.....................................................................................................................................18 5. EXTERNAL CLOCK INPUT INTERFACE.................................................................................................................18 DC CHARACTERISTICS ....................................................................................................................................19
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MX88L250EC
Revision: 0.03A 2001/10/12
1. ENVIRONMENTAL SPECIFICATION: .....................................................................................................................19 2. STANDARD DC SPECIFICATION FOR 3.3 VOLTS OPERATION:...............................................................................19 DIMENSION .........................................................................................................................................................20
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MX88L250EC
Revision: 0.03A 2001/10/12
General Description
MX88L250EC Series is the Low Cost yet High Performance Solution for Flat Panel Display application. Applying Macronix' s SmartscalingTM-2+ filter, it provides high quality scaled video image and format conversion capability.
Applications
*
XGA/SXGA LCD monitors
Features
General Features * MX88L250EC-X and MX88L250EC-S are fully Pin to Pin Compatible. * * * * * * * * * * * * * Input
Convert PC video signal into flat panel display device timing and resolution. Built-in Line Buffer to provide Fame-Buffer-Less solution. Support Clock, Phase, Horizontal and Vertical position adjustments. Support Auto-Tracking and Auto-Position capabilities (SmartTrackingTM Technology). Support Auto-Gain capability for input image Arbitrary scaling from 1 to 32 times with filters (SmartScalingTM - 2+ Technology). Support Edge Filter control. Built-in OSD generator with 64 ROM /128 programmable RAM fonts, mixer with Color Palette, Color Key and Alpha Blending. Provide 90-degree Rotation for internal OSD to support Portrait direction display. On-chip Digital Brightness and Contrast adjustments. On-chip Digital Gamma Correction for panel compensation. Support Temporal Dithering capability to make 18 bit video as good as 24 bit quality. Support " Test mode" function which internally generates some test patterns, including gray, saw, and cross talk, for output.
* *
MX88L250EC-X supports Single port 24bit, PC video up to XGA operation mode. MX88L250EC-S supports Single port 24bit, PC video up to SXGA operation mode.
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MX88L250EC
Revision: 0.03A 2001/10/12
* * * * Output *
MX88L250EC-D supports Dual port 48bit, PC video up to SXGA operation mode Support Composite Sync. input. Support H/V Sync. Polarity and Pulse Width information for mode detection. Support H/V Sync. Interrupt for power management requirement.
Support TFT LCD panel in following resolution and frequency. 800x600 20 ~ 55 50 ~ 75 32.5 ~ 60 1024x768 20 ~ 70 50 ~ 75 25 ~ 80 1280x1024 80 75 140
Resolution Horizontal frequency (KHz) Vertical frequency (Hz) Dot clock (MHz)
* * * * CPU Interface * * * Power * *
Single (18/24) and Dual (36/48) bit RGB data output. Support Inverse, Delay and Frequency adjustments for LCD panel clock. Support programmable H/V sync. and LDTG timing for LCD panel. Support two PWM outputs
Support Direct Bus 8 bit interface (MX88L250EC-D only) Support Two/Three-Wire Serial Bus interface. Support Double Buffer Register capability.
Power Supplier: Dual Power 3.3/2.5 volts, 5V tolerant inputs. Power Consumption: less than 1W.
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MX88L250EC
Revision: 0.03A 2001/10/12
Chip Block Diagram
PIXIN (RGB24/48)
Auto-Tracking Auto-Position Auto-Gain Mode Detection
Scaling Engine Smart-Scaling 2+
OSD Generator
X' ta l
PLL
Brightness Contrast Gamma Correction Dithering
ODD / EVEN MUX
PIXOUTA (RGB) PIXOUTB (RGB)
MCU
BIU
OSD MUX
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MX88L250EC
Revision: 0.03A 2001/10/12
System Block Diagram for LCD monitor ( TTL and PanelLink / LVDS Interfaced )
Analog Interface LCD monitor
RGB 24/48bit
ADC/PLL
Vsync Hsync Pix-In Dclk
MX88L250 EC
TTL/LVDS/ Panel-Link Interface
FPD Panel
Vsync Hsync Pix-Out Dclk
X' ta l
MCU
Digital Interface LCD monitor
RGB 24/48bit
DVI Rx.
Vsync Hsync Pix-In Dclk DDE
MX88L250 EC
TTL/LVDS/ Panel-Link Interface
FPD Panel
Vsync Hsync Pix-Out Dclk
X' ta l
MCU
7
MX88L250EC
Revision: 0.03A 2001/10/12
MX88L250EC-X, MX88L250EC-S 128p Pin Configurations
PIXINA0 PIXINA1 PIXINA2 PIXINA3 PIXINA4 PIXINA5 PIXINA6 PIXINA7 VDD PIXINA8 PIXINA9 PIXINA10 PIXINA11 GND PIXINA12 PIXINA13 PIXINA14 PIXINA15 VDDP PIXINA16 PIXINA17 PIXINA18 PIXINA19 PIXINA20 PIXINA21 PIXINA22
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
GNDP DCLKA GND BUSTYPE1 NC VDDP AVDD2 AVDD1 XI XO AGND1 AGND2 GNDP DDE GNDP HSYNC2 CLAMP VSYNC1 HSYNC1/CS VDD TDCLK/SOGCS GNDP TRCLK/HSI_OUT VDDP IRQ RST# BCS VDDP GPIOA4/PDEN GPIOA3 GPIOA2 GPIOA1/PWM1 GPIOA0/PWM0 GNDP SBCLK/I2CCLK SBDATA/I2CDATA SBCS# GND
MX88L250EC-X (XGA FBL) MX88L250EC-S (SXGA FBL) PQFP128 (preliminary)
RA0 VDD RA1 RA2 RA3 RA4 RA5 RA6 RA7 VDDP GA0 GA1 GA2 GA3 GNDP GA4 GA5 GA6 GA7 BA0 BA1 BA2 BA3 BA4 BA5 BA6
PIXINA23 VDD BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 GNDP GB7 GB6 GB5 GB4 VDDP GB3 GB2 GB1 GB0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 GND GNDP LCKA VDDP LCKB GNDP LHSYNC LVSYNC LDTG BA7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
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MX88L250EC
Revision: 0.03A 2001/10/12
MX88L250EC-D 160p Pin Configurations
PIXINA5 PIXINA6 PIXINA7 PIXINB0 PIXINB1 PIXINB2 PIXINB3 PIXINB4 PIXINB5 PIXINB6 PIXINB7 VDD PIXINA8 PIXINA9 PIXINA10 PIXINA11 PIXINA12 PIXINA13 PIXINA14 PIXINA15 GND PIXINB8 PIXINB9 PIXINB10 PIXINB11 PIXINB12 PIXINB13 PIXINB14 PIXINB15 VDDP PIXINA16 PIXINA17 PIXINA18 PIXINA19 PIXINA20 PIXINA21 PIXINA22 PIXINA23 PIXINB16 PIXINB17
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PIXINA4 PIXINA3 PIXINA2 PIXINA1 PIXINA0 GNDP DCLKA GND BUSTYPE1 BUSTYPE0 VDDP AVDD2 AVDD1 XI XO AGND1 AGND2 GNDP DDE GNDP HSYNC2 CLAMP VSYNC1 HSYNC1/CS VDD TDCLK/SOGCS GNDP TRCLK/HSI_OUT VDDP IRQ RST# BCS VDDP GPIOA4/PDEN GPIOA3 GPIOA2 GPIOA1/PWM1 GPIOA0/PWM0 GNDP AD7/SBCLK/I2CCLK
MX88L250EC-D (SXGA FBL) PQFP160 (preliminary)
AD6/SBDATA/I2CDATA AD5/SBCS# GND AD4 AD3 AD2 AD1 AD0 RD# WR# ALE RA0 VDD RA1 RA2 RA3 RA4 RA5 RA6 RA7 VDDP GA0 GA1 GA2 GA3 GNDP GA4 GA5 GA6 GA7 BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 LDTG LVSYNC
PIXINB18 PIXINB19 PIXINB20 PIXINB21 PIXINB22 PIXINB23 VDD BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 GNDP GB7 GB6 GB5 GB4 VDDP GB3 GB2 GB1 GB0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 GND GNDP LCKA VDDP LCKB GNCP LHSYNC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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MX88L250EC
Revision: 0.03A 2001/10/12
General Description
There are three major portions in this chip which include VIP (Video Input Processor), VOP (Video Output Processor) and BIU (CPU Bus Interface Unit). Following is the block and description of these portions.
Line Buffer
Digital RGB
VOP
FPD Panel
VIP BIU OSD
uP
Fig. Chip Level Block Diagram
VIP (Video Input Processor) Function Description
VIP is a video input process unit which receives digital data from ADC or digital input then process it to line buffer for VOP. It supports mode detection, auto-position, auto-gain, auto-tracking function for ADC modification.
VOP (Video Output Processor) Function Description
VOP is a Video Output Process unit which reads data from line buffer and then process it to flat panel display. With Line Buffers and Scale- up logic based on proprietary SmartscalingTM -2+ algorithm, it can enlarge image smoothly. Furthermore, it provides many adjusting functions like programmable Brightness and Contrast control, programmable GAMMA table, programmable Dithering control, and OSD MUX to adjust the output quality. It also provides Single/Dual output to cope with different flat panels display device.
BIU (Bus Interface Unit) Function Description
BIU is a bus interface unit between the host CPU and MX88L250 which supports two bus types: Direct and Serial Bus.
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MX88L250EC
Revision: 0.03A 2001/10/12
Pin Description
CPU Interface Pins: (8 / 16 pins)
Pin Name Drive I/O Pin No.
(L250EC-X) (L250EC-S) 128 pin
Pin No.
(L250EC-D) 160 pin
DESCRIPTION
RST# AD[7:0]
I IO
77 X
90 81-79 77-73
System reset. Multiplexed low order address and data bus
SBCLK / AD7
I
68
81
80
Two/Three-Wire Serial Bus Clock (share with AD7)
SBDATA / AD6
IO
67
Two/Three-Wire Serial Bus Data (share with AD6)
SBCS# / AD5
I
66
79
Three-Wire Serial Bus CS# (low active) (share with AD5)
BCS ALE WR# RD# BUSTYPE1 BUSTYPE0 IRQ
I I I I I I O
76 X X X 99 98 78
89 70 71 72 112 111 91
Bus Select, Active high. Address Latch Enable for 8051 Bus. Memory Write Strobe for direct bus Memory Read Strobe for direct bus Bus type bit 1 Bus type bit 0 (NC for MX88L250EC-S & -X) Interrupt request
Input Interface Pins: (29 / 53 pins)
Pin Name Drive I/O Pin No.
(L250EC-X) (L250EC-S) 128 pin
Pin No.
(L250EC-D) 160 pin
DESCRIPTION
PIXINA 0-7 PIXINA 8-15
I I
103-110 112-115 117-120
116-123 133-140
Input data R0-R7 Input data G0-G7
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MX88L250EC
Revision: 0.03A 2001/10/12
Pin Name
Drive
I/O
Pin No.
(L250EC-X) (L250EC-S) 128 pin
Pin No.
(L250EC-D) 160 pin
DESCRIPTION
PIXINA 16-23
I
122-128 1
151-158
Input data B0-B7
PIXINB 0-7 PIXINB 8-15 PIXINB 16-23
I I I
X X X
124-131 142-149 159-160 1-6
Input data R0-R7 Input data G0-G7 Input data B0-B7
HSYNC1/CS
I
84
97
Hsync input1 (for mode detection)
HSYNC2
I
87
100
Hsync input2 (for screen position & sampling use)
VSYNC1 DDE DCLKA
I I I
85 89 101
98 102 114
Vsync input Digital Data enable Input dot clock1
LCD Interface Pins: (53 pins)
Pin Name Drive I/O Pin No.
(L250EC-X) (L250EC-S) 128 pin
Pin No.
(L250EC-D) 160 pin
DESCRIPTION
RA[7:0]
4 mA
O
64 62-56
69 67-61 59-56 54-51 50-43 33-26 25-22 20-17 15-8 41
RED DATA (Odd),
GA[7:0]
4 mA
O
54-51 49-46
GREEN DATA (Odd),
BA[7:0] RB[7:0] GB[7:0]
4 mA 4 mA 4 mA
O O O
45-38 28-21 20-17 15-12
BLUE DATA (Odd), RED DATA (Even). GREEN DATA (Even).
BB[7:0] LVSYNC
4 mA 8 mA
O O
10-3 36
BLUE DATA (Even), VSYNC output for LCD display.
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MX88L250EC
Revision: 0.03A 2001/10/12
Pin Name
Drive
I/O
Pin No.
(L250EC-X) (L250EC-S) 128 pin
Pin No.
(L250EC-D) 160 pin
DESCRIPTION
LHSYNC LDTG LCKA LCKB
8 mA 8 mA 16 mA 16 mA
O O O O
35 37 31 33
40 42 36 38
HSYNC output for LCD display. Data Enable output for LCD display. Odd data clock output for LCD display Even data clock output for LCD display.
Internal VCG Interface Pins: (2 pins)
Pin Name Drive I/O Pin No.
(L250EC-X) (L250EC-S) 128 pin
Pin No.
(L250EC-D) 160 pin
DESCRIPTION
XI XO
I O
94 93
107 106
Analog pad for Reference Frequency Input for internal oscillator. (3.3 V) Analog pad for Reference Frequency Output for internal oscillator. (3.3V)
Other Interface Pins: (6 pins)
Pin Name Drive I/O Pin No.
(L250EC-X) (L250EC-S) 128 pin
Pin No.
(L250EC-D) 160 pin
DESCRIPTION
GPIOA0 / PWM0 GPIOA1 / PWM1 GPIOA2 GPIOA3 GPIOA4 / PDEN Clamp
2 mA
IO
70
83
Pulse width Modulation 0 Output, share with general IO 0
2 mA
IO
71
84
Pulse width Modulation 1 Output, share with general IO 1
2 mA 2 mA 2 mA
IO IO IO
72 73 74
85 86 87
General IO 2 General IO 3 PDEN output for ADC Shared with general IO 4
O
86
13
99
Clamp output for ADC
MX88L250EC
Revision: 0.03A 2001/10/12
External Clock Input Interface Pins: (2 pin)
Pin Name Drive I/O Pin No.
(L250EC-X) (L250EC-S) 128 pin
Pin No.
(L250EC-D) 160 pin
DESCRIPTION
TRCLK / HS1_OUT TDCLK / SOGCS
I O I
80
93
External RCLK input (share with HS_OUT)
82
95
External DCLK input. (share with SOGCS)
Power Pins: (28 pins) dual power 3.3 / 2.5 Volts, 5 Volt tolerant inputs
Pin Name Drive I/O Pin No.
(L250EC-X) (L250EC-S) 128 pin
Pin No.
(L250EC-D) 160 pin
DESCRIPTION
VDD
2,63,83, 111,
7,68,96, 132, 34,78,113, 141, 21,37,60, 88,92,110, 150,
Core Power 2.5 V
GND
29,65, 100,116
Core GND
VDDP
16,32,55 ,75,79,9 7,121 11,30,34 ,50,69,8 1,88,90, 102,
PAD Power 3.3 V
GNDP
16,35,39, 55,82,94, 101,103, 115,
PAD GND
AVDD1 / AVDD2 AGND1 / AGND2
95,96 91,92
108,109 104,105
Analog Power 2.5 V Analog GND
Remark: 1. All the input loading is 5pf 2. Driving capability is measured under 20pf loading 3. LCKA driving capability is measured under 30pf loading
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MX88L250EC
Revision: 0.03A 2001/10/12
AC Characteristics
1. Input signal
DCLKA
TIS0S VS1,HS1
TIS0H
DCLKA
TIS1S PIXINA23-0
TIS1H
Symbol TIS0S, TIS0H TIS1S, TIS1H
Parameter Setup time Hold time
Min. 2 2
Max.
Unit ns ns
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MX88L250EC
Revision: 0.03A 2001/10/12
2. Output signal
LCK
LVSYNC LHSYNC LDTG
TOS1DL(max.)
TOS1DL(min.)
RA[7:0] RB[7:0] GA[7:0] GB[7:0] BA[7:0] BB[7:0]
TOS2DL(max.)
TOS2DL(min.)
Symbol TOS1DL TOS2DL
Parameter Output LHSYNC, LVSYNC, LDTG output delay Output Pixel Signal output delay
Min. 1 1
Max. 5 5
Unit ns ns
16
MX88L250EC
Revision: 0.03A 2001/10/12
3. Direct CPU Interface
TWHLH
ALE TLLWL TWLWH
WR/RD
TAVLL TLLAX TWSQX
TWHQX
AD(7:0)/WR
A0-A7
DATA OUT
A0-A7
TAVWL
AD(7:0)/RD
A0-A7
DATA OUT
TRRS
TRDLY
TRDOFFF
Symbol TAVLL TLLAX TWLWH TWSQX TWHQX TWHLH TRDLY TRDOFF
Parameter Address Valid to ALE Low Address Hold After ALE Low WR Pulse Width Data Setup Before WR Data Hold After WR WR/RD High to ALE High Data delay after RD Low Data off delay after RD High
Min. 2 1 30 10 0 0 10 0
Max.
Unit ns ns ns ns ns ns
35 7
ns ns
17
MX88L250EC
Revision: 0.03A 2001/10/12
4. Serial Bus Interface
Symbol Tcsck Tckcs Tds Tdh Tdd
Parameter CS to CLK Start CLK to CS high Data setup time versus CLK Data hold time versus CLK Data delay time
Min. 0 20 10.1 20 14
Max.
Unit ns ns ns ns
18
ns
5. External Clock Input Interface
Symbol Fclk Fpw Parameter Maximum TDCLK input frequency Minimum pulse width 3 Min. Max. 80 Unit MHz ns
18
MX88L250EC
Revision: 0.03A 2001/10/12
DC characteristics
1. Environmental specification:
Rating Ambient Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature Value 0 to 70 -55 to 125 125 100 Unit C C C C
2. Standard DC Specification for 3.3 Volts Operation:
(Ta=0C to 70C, VCC=3V to 3.6V) Symbol VOH VOL VIH VIL RPU RPD ILI ILO Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage I/O Pull-up Resistance I/O Pull-down Resistance Input Leakage Current Output Leakage Current 100 50 -10 -20 2.0 0.8 300 150 +10 +20 Min 2.4 0.4 Max Unit V V V V KOhm KOhm uA uA Conditions
19
MX88L250EC
Revision: 0.03A 2001/10/12
Dimension
D 28.00 0.05 ZD D3
DETAIL "A" 144F2828-A 160F2828-A208F2828-A 256F2828-A
b
0.32 0.10 0.30 0.65 1.60 0.80 1.33 25.35
0.32 0.10 0.30 0.65 1.60 0.80 1.33
0.22 0.10 0.20 0.50 1.30
0.18 0.10 0.16 0.40 1.30 0.50 1.25 25.50 30.6 1.40 25.20 30.6 0.35 3.80 256L
MO-143 FB1
15
3E3 2 8 .0 0 0 .0 5 E R 0.15
C b1 e L1 L
10 L
R 0.20 5
ZE (REF.) E3 (REF.) E ZD (REF.) D3 (REF.) D A1 A (MAX.) N
JEDEC
DETAIL "A"
25.35 31.2 1.33 25.35 31.2
0.35
0.50 1.25 25.50
30.6 1.25 25.50 30.6 0.35 3.80 208L
MO-143 FA-1
DETAIL "B" 2 .5 4
N
L1
31.2 2.63
25.35
ZE
TERMINAL DETAILS
31.2 0.35 3.80 144L
MO-108 DC-1
2.54
DATUM PLANE
BASE PLANE
0.10MM
1.60
12
3.80 160L
MO-108 DD-1
SEATING PLANE
b
e
A1
0 .1 5 T Y P .
b
C
WITH PLATING
BASE METAL b1
DETAIL "B"
DETAIL "A"
Macronix International Co., Ltd. TITLE OUTLINE DIMENSIONS FOR QFP2828 MM PACKAGE APPROVED SCALE UNIT
e /2
A
DWG. NO.
6110-0212 TOLERANCE
ANGLE
DRAWN
CH Lin
JW Lin
mm
REVISION 2
20
MX88L250EC
Revision: 0.03A 2001/10/12
21

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